1. Technical Field
The present invention relates to an input buffer for a semiconductor memory apparatus. In particular, the present invention relates to a technique that is adapted for an input buffer for a very high speed semiconductor memory apparatus having low power consumption by increasing a response speed with respect to an input signal.
2. Related Art
In general, a semiconductor memory apparatus uses an input buffer so as to receive data, and external signals, such as an address signal, a control signal, and the like. An input buffer circuit converts a voltage at a TTL (Transistor Transistor logic) level that is applied from the outside the semiconductor memory apparatus into a voltage at a CMOS (Complementary Metal Oxide Semiconductor) level on the basis of the environment in chips.
It is well known that the speed at which internal circuits of the semiconductor memory apparatus operate has currently been increased such that a semiconductor memory apparatus enables high frequency operation using low power.
With the technical trend of the semiconductor memory apparatus, the input buffer also has a circuit structure adapted for a low power environment and at the same time, increases the response speed with respect to an input signal. Therefore, the input buffer has contributed to low power consumption and high speed access of the chips.
In general, an input buffer having the above-described characteristics has a structure of a differential amplifier of the type of a current mirror.
FIG. 1 is a circuit diagram illustrating an input buffer according to the related art.
As shown in FIG. 1, an input buffer according to the related art includes a driving control unit 10, a buffer unit 20, and an output driver 30.
The driving control unit 10 includes an inverter IV1 that inverts an input control signal ctrl1 and outputs an inverted control signal ctrl1b. 
The buffer unit 20 includes a structure that performs differential amplification of an input signal in1 and a reference signal vref1. The buffer unit 20 includes a plurality of PMOS transistors, P1 to P4, and a plurality of NMOS transistors, N1 to N3, that have a current mirror structure. More specifically, the plurality of PMOS transistors P1 to P4 have a common source terminal to which a power supply voltage VDD is applied, the PMOS transistors P1 and P2 have a common drain terminal connected to the NMOS transistor N1, and the PMOS transistors P3 and P4 have a common drain terminal connected to the NMOS transistor N2. Each of the PMOS transistors P1 and P4 has a gate terminal to which the control signal ctrl1b, that is, the output of the driving control unit 10, is applied. Each of the PMOS transistors P2 and P3 has a gate terminal connected to the NMOS transistor N2.
In addition, the NMOS transistors N1 and N3 are connected in series between the PMOS transistor P2 and a ground voltage terminal VSS. Here, the NMOS transistor N1 has a gate terminal to which the input signal in1 is applied, and the NMOS transistor N3 has a gate terminal to which the inverted control signal ctrl1b is applied. The NMOS transistor N2 is connected between the PMOS transistor P3 and the NMOS transistor N3, and has a gate terminal to which a reference voltage vref1 is applied.
The output driver 30 includes inverters IV2 and IV3 that are connected in series. The inverter IV2 inverts a signal at a node c1, which is an output of the buffer unit 20, and outputs the inverted signal to a node d1. The inverter IV3 inverts a signal at the node d1 and outputs an output signal out1.
Operation of the input buffer according to the related art that has the above-described structure will be described with reference to FIG. 2, which is an operation timing chart.
Throughout the specification to be described in detail below, it is assumed that the power supply voltage VDD is 1.6 V, a logical high level is correspondingly 1.6 V, and the reference voltage vref1 is approximately 0.8 V.
First, when the input control signal ctrl1 changes to a high level (that is, 1.6 V), the inverted control signal ctrl1b changes to a low level. The NMOS transistor N3 for activating the buffer unit 20 is turned off, and thus the input buffer does not operate.
Then, when the control signal ctrl1 changes to a low level (that is, 0 V), the inverted control signal ctrl1b changes to a high level. The NMOS transistor N3 is turned on, and thus the input buffer operates.
Further, the buffer unit 20 compares the reference voltage vref1 and a voltage of the input signal in1, and outputs a result of the comparison to the node c1. That is, when the power supply voltage VDD is 1.6 V and the ground voltage VSS is 0 V, the reference voltage vref1 becomes 0.8 V, which corresponds to an intermediate level between the power supply voltage VDD and the ground voltage VSS.
Therefore, when the voltage of the input signal in1 is higher than the reference voltage vref1, the current flowing through the NMOS transistor N1 increases, and thus the node c1 changes to a low level. On the other hand, when the voltage of the input signal in1 is lower than the reference voltage vref1, the current flowing through the PMOS transistor P2 and the NMOS transistor N2 increases, and thus the signal at the node c1 changes to a high level.
Then, the output driver 30 amplifies the signal at the output node c1 of the buffer unit 20 into the output signal out1. The inverters IV2 and IV3 non-inversely delay the signal at the node c1, and output the output signal out1.
Referring to FIG. 2, in an input buffer according to the related art, the buffer unit 20 operates at a point of time (A) (that is, 10 ns) when the input signal in1 changes from a high level to a low level, and the signal at the node c1 changes from a low level to a high level (10.8 ns).
However, in the buffer unit 20, since a potential changes according to a change in current, it takes a long time for the signal at the node c1 to change from a low level to a high level. In order to solve this problem, an operation speed of the buffer unit 20 may be improved by increasing the size of the NMOS transistor N3. In this case, however, the current consumed by the buffer unit 20 increases.
As a result, since it takes approximately 1.3 ns for the input signal in1 (10 ns) to be output as the output signal out1 (11.3 ns), there is a limit on improving the operation speed of an input buffer that needs to operate quickly.